HY64LD16162M sram equivalent, 1m x 16 bit low low power 1t/1c pseudo sram.
* CMOS Process Technology
* 1M x 16 bit Organization
* TTL compatible and Tri-state outputs
* Deep Power Down : Memory cell data hold invalid
* Standa.
- Power Up & Deep Power Down Exit Sequence Mar. 11. ‘ 02 Final Feb. 27. ‘ 02 Preliminary Dec. 20. ‘ 01 Preliminary Nov. 14. ’ 01 Preliminary Oct. 07. ‘ 01 Preliminary Jul.18. ’ 01 Preliminary
Draft Date
Jan. 04. ’ 01 Jul. 03. ’ 01
Remark
Preliminar.
Image gallery
TAGS
Manufacturer
Related datasheet